The present invention relates to a semiconductor device of multi-level wiring structure such as a logic LSI (Logical Large Scale Integrated Circuit), a DRAM (Dynamic Random Access Memory), SRAM (Static RAM), a CMOS (Complementary Metal Oxide Semiconductor) or a bipolar transistor (Bipolar Transistor), especially, to a formation of multi-level wiring which includes via-contact formation using wiring formation and a conductive pillar-shaped structure (pillar), and a semiconductor device which has a multi-level wiring structure.
Conventionally, in general, when a connection plug, which electrically connects between the wirings of the upper level and the lower level in the multi-level wiring structure of the semiconductor device, is formed, a method of opening a contact hole by using a reactive ion etching (RIE (Reactive Ion Etching)) method etc. for an interlevel insulation film, and forming the connection plug by burying a conductive material such as metal is used.
This conventional art has the following disadvantages. At the RIE for the opening of the contact hole, physical damage and corrosion are caused on the surface of lower level wiring exposed to the bottom of the contact hole with the etching gas and the sputtered particle. A contact resistance between the above-mentioned connection plug and the lower level wiring rises by adhering the etching residue and the sputtered particle. When the contact hole is not formed at a desired position by the occurrence of the missalignment with the lower wiring pattern at formation of the contact hole, the lower wiring side and the interlevel insulation film thereunder are excessively etched by RIE. In addition, the undesirable short-circuit with the wiring of the lower level is occurs, and the cave remains around a fine wiring. As a result, the reliability lowers.
When the lower level wiring is formed, a method of forming a conductive pillar-shaped structure (pillar) and the lower level wiring at the same time is known. This method is a method of depositing a metal film on the insulation film formed on the semiconductor substrate, forming the connection plug with a photo-lithography and the etching methods such as an RIE and leaving a metal film in the trench to form the lower level wiring. However, the lower level wiring is the same material as the connection plug, and changing both of the material cannot broaden the variety of the selection of the material. Moreover, when the connection plug is etched, the lower level wiring might be over-etched. In addition, the missalignment might be occurred when the connection plug and the upper level wiring are connected.
Recently a high speed operation has come to be requested to the device. Therefore, a lower resistance material is required as for the wiring material. Copper (Cu) has been paid attention so as to respond to the request and is multi-used. The electrical resistivity of the copper is 1.8 .mu..OMEGA.cm, and it is greatly low among the wiring material. Besides this, tungsten (W) whose resistivity is 10 to 20 .mu..OMEGA.cm and aluminum (Al) whose resistivity is 3 to 4 .mu..OMEGA.cm are used well as a wiring material. Therefore, AlCu alloy is used as any of the lower level wiring 12, the connection plug 14 (conductor pillar), and the upper level wiring 18 shown in FIG. 1A and FIG. 1B, for example, but is considered that the wiring resistance is reduced by using Cu for the lower level wiring 12 and the upper level 18, and using Al for the connection plug 14.
However, the.inconvenience might happen when Cu is used as it is. First, Cu has characteristics to diffuse into the insulation film in the state of the atom when Cu is covered by the insulation film. Especially, the moving of Cu becomes active if Cu is heated by the use of the device and the heat-treating step under manufacturing, then the wiring is destroyed and comes to cause the disconnection and the short-circuit accident easily. Moreover, the surface is oxidized when Cu is exposed in (the) air, and advantage of the low resistance is lost.
Moreover, in the above-mentioned pillar technology, since the pillar-shaped structure (pillar) is formed only to connection part of the lower level wiring and the upper level wiring, the ratio of the region where the pillar-shaped structure is formed becomes very small and is about several % or less of the whole. Therefore, the pillar-shaped structure is excessively etched, for example, when the drying etching, and the processing of the pillar-shaped structure becomes difficult. The planarity of the interlevel insulation film formed after processing of the pillar-shaped structure deteriorates.
As described above, since the ratio of the region where the pillar-shaped structure is formed is very small when the pillar technology is used for the connection of the lower level wiring and the upper level wiring, there is a subject matter of a bad processing control of the pillar-shaped structure and a bad planarity of the interlevel insulation film.